As integrated circuit (IC) technology shrinks and current densities increase, the current-carrying capacity of metallic conductive paths, such as metal wires and vias, is stretched to its limits. High current densities can cause metal wires and vias to develop defects, such as voids or shorts, over long periods of operation due, for example, to electromigration, joule-heating, or fusing. Products incorporating integrated circuits that develop such defects may fail in use.
Prior techniques to deal with such difficulties have included use of manual methods (for example, with respect to power ICs) to estimate high current density regions, with concomitant addition of conductive material to such regions. Manual methods are not feasible for use with large and complex ICs, such as high-density mixed-signal ICs which carry large currents and are expected to work reliably at high operating temperatures over many years. Automated methods might employ reliability analyses performed on discretized elements rather than actual geometric representations of pertinent metallic conductive paths. Prior techniques, manual and automated, may be overly pessimistic and result in an overly conservative design. Numerous false indications of failure, requiring manual correction, may negate any benefit from automated techniques.
Because of these disadvantages, methods and apparatus that allow, e.g., automated detection and/or accurate reliability analysis of potential trouble spots, such as high current density areas, would be advantageous.